Effect of elastic processes and ballistic recovery in silicon nanowire transistors

Abstract

Scaling of silicon devices is fast approaching the limit where a single gate may fail to retain effective control over the channel region. Of the alternative device structures under focus, silicon nanowire transistors (SNWT) show great promise in terms of scalability, performance, and ease of fabrication. Here we present the results of self-consistent, fully 3D quantum mechanical simulations of SNWTs to show the role of surface roughness (SR) and ionized dopant scattering on the transport of carriers. We find that the addition of SR, in conjunction with impurity scattering, causes additional quantum interference which increases the variation of the operational parameters of the SNWT. However, we also find that quantum interference and elastic processes can be overcome to obtain nearly ballistic behavior in devices with preferential dopant configurations.