Abstract
Anomalous capacitance-voltage behavior of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi/sub 2/ layer is reported. The C-V characteristics and specifically the inversion and accumulation capacitances are gate-bias-dependent and are strongly affected by annealing temperature, silicidation, and polysilicon gate microstructure (i.e. polysilicon versus amorphous gate). The results can be explained by insufficient As redistribution, coupled with carrier trapping, and As segregation at polysilicon grain boundaries and in TiSi/sub 2/. All these effects lead to the formation of a depletion region in the polysilicon gate and thus to the anomalous C-V behavior.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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