Abstract
A high-speed comparator design based on regeneration architecture, which can be used in a flash ADC, is presented. A threshold-limit-speed effect (TLSE) which limits the speed of the comparator was discovered and studied in detail. The size of the reset-MOSFET was optimized to resolve the TLSE and make the comparator work at the maximal speed. The results were confirmed by simulation and the corresponding circuit was realized in a flash ADC design in SMIC 0.18-μm CMOS technology. The test result shows that the comparator can work well at 2 GHz and can even work up to 2.8 GHz while the power dissipation is 3.2 mW.
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