Economic analysis of test and known good die for multichip assemblies

Abstract

The cost and quality of a multichip assembly is highly dependent upon the cost and quality of the incoming die. In the case of a bare die assembly, it is often highly desirable to use either Known Good Die (KGD) or die that have been burned-in and tested to the same level of quality and reliability as their packaged die equivalents. However, performing full bare die burn-in and test may not always be cost effective. This paper examines the question of whether it is always necessary to use KGD to produce a cost-effective multichip module (MCM) of acceptable quality. A process-flow based cost model is used to compare the cost and quality of MCMs assembled with KGD to MCMs assembled with die that have received wafer-level test only. In addition to test effectiveness at the wafer, die, and module level, factors that are considered include die complexity (size and I/O), number of die per MCM, the cost of producing the KGD, and rework costs and effectiveness. The cost model captures inputs from wafer fabrication through MCM assembly and rework. Monte Carlo simulation is used to account for uncertainty in the input data. The resulting sensitivity analyses give final MCM cost and quality as a function of the various factors for both KGD and die that have received wafer-level test only