Abstract

The presence of Ventricular Late Potentials (VLP) in an Electrocardiographic signal (ECG) is associated with possible sudden cardiac death, caused by malignant arrhythmia. An effective VLP detection is strongly influenced by the signal noise, thus the ECG needs to be denoised before VLP detection. The objective of this paper is to define a denoising algorithm for enhancing VLP detection in ECGs, useful for implementation on a Field Programmable Gate Array device (FPGA). The method described uses wavelet denoising, implemented as subband coding. The drawbacks of this method are heavy linear distortions undergone by the analyzed signal. This disadvantage is overcome by using an equalization filter for canceling the introduced distortions. The algorithm is defined using MATLAB, then its hardware implementation is designed and simulated in Altera's Quartus software. The synthesized hardware is then verified on the evaluation board DE1-SoC by Terasic, mounting a Cyclone V Intel - Altera FPGA chip. On board processed results and theoretical results are consistent, validating the effectiveness of the designed hardware. Results show that such design could be used for upgrading ECG devices reliability in the field of heart diseases prevention.

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