Abstract
Aging effects in advanced technologies produce significant performance degradation as time progresses. In order to guarantee safe operation, aging-delay monitors can be inserted at the output nodes of critical paths (CPs) to allow predictive error detection. However, online monitoring of a large number of CPs that can exist in the state-of-art designs is not feasible. The conventional statistical selection of CPs requires knowledge of the coordinates of each gate in the corresponding layout of the circuit to account for spatial correlation between devices’ process parameters. This paper presents a nonspatial-correlation-dependent methodology to select the CPs for aging-delay monitoring for predictive error detection. Spatial correlation is bounded by a statistical approach maximizing CPs’ coverage. The proposed early selection methodology is validated by comparing the obtained results with those obtained with the availability of spatial correlation information extracted from the circuit layout. The results clearly show that the set of CPs selected with the proposed early selection methodology is in good agreement with the one selected with the availability of layout information. Therefore, our proposed methodology is very attractive to be used in the early design stages, where detailed circuit layout is not available.
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More From: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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