Early analysis of chip scale package design trade-offs

Abstract

Chip scale packages (CSPs) present new challenges for both package designer and package user. It is possible to make package design trade-offs between package size, I/O pattern, thermal/electrical performance and cost for a given IC. An ideal set of CSP design trade-offs for one application may be a poor selection for another. Early analysis tools give technical information needed to select and design the best package for any given application. The long development cycles of a new package technology, combined with ever decreasing product design cycle times, place a premium on generating early analysis information. The chip scale package design and evaluation system (CSPDES) was designed to provide this critical early analysis information to package designers and potential customers. The CSPDES starts with users entering IC component level information into the system. It then provides a selection of possible CSPs. The user selects a CSP and completes an interconnect pattern between IC bonding pads and package signal or power pins. Once the package is interconnected, the system provides electrical and thermal information to define operation in the user's application. It is also possible to select alternative packages to determine the best trade-offs between size, electrical properties, thermal properties and cost. A special feature of the CSPDES is a unique, easy to operate client/server interface. Engineers with access to the system can perform a detailed package analysis early in the design process. Once analysis is complete, system outputs go to physical design CAD tools which complete the package design process.