Abstract
A novel dataline redundancy suitable for an embedded DRAM macro with wide data bus is proposed. This redundancy saves an area of spare cells from 6% to 1.6% and improves chip yield from 50% to 80%. It provides high speed data path. An embedded DRAM macro adopting the redundancy achieves 200 MHz operation and provides 51.2 Gbit/sec bandwidth. It has been fabricated with 0.25 /spl mu/m technology.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.