Abstract
Information security is the foundation for building trust between the Internet of Things (IoT) and its users. Due to the sharp increase of information quantity and the limitation of hardware resources, it is difficult to maintain the high performance of hardware equipment, while also enhancing information security. To solve the problem of high consumption and low flexibility of multiple cryptographic algorithms hardware implementation, we have designed the Dynamically Reconfigurable Encryption and Decryption System, which is based on Field Programmable Gate Array. Considering the functional requirements, the cryptographic algorithm reconfigurable module files stored in External Memory could be configured dynamically into the assigned on-chip Reconfigurable Partition, supported by Core Controller and the Reconfiguration Control Platform. The experiment results show that, compared with the Static Encryption and Decryption System, our design reduces the logic resources by more than 30% and completes the algorithm swapping at the configuration speed of 15,759.51 Bytes/ms. It indicates that our design could reduce logic resources consumption and improve utilization efficiency and system flexibility.
Highlights
In recent years, the rapid development of the Internet and communication technology has resulted in intelligent devices penetrating every aspect of human life [1]
The DREDS designed in this paper includes two parts: One, the reconstruction function supported by the Static Partition (SP) and two, the algorithm reconfiguration realized by Reconfigurable Partition (RP)
In order to improve the information security and hardware processing performance of the Internet of Things (IoT), we proposed multiple algorithms that support DREDS with high flexibility and high resource utilization, as well as the implementation of the Xilinx’s ZYNQ-7000 series of the Field Programmable Gate Array (FPGA)
Summary
The rapid development of the Internet and communication technology has resulted in intelligent devices penetrating every aspect of human life [1]. Compared with the Application Specific Integrated Circuit (ASIC) and the digital signal processor (DSP), Field Programmable Gate Array (FPGA), a semi-custom circuit in the ASIC field, reduces the development cycle of custom circuit, and overcomes the shortcomings of the original programmable device limited gates It has the advantages of fast processing speed, rich functions, high flexibility, and ultra-low power consumption. In order to enhance information security and hardware implementation performance of IoT, the encryption and decryption system based on dynamically reconfigurable technology provides a solution. This paper optimizes the implementation of AES, 3DES algorithm, and the Static Encryption and Decryption System (SEDS), as well as enriches the data of hardware resources utilization. It is worth mentioning that we proposed the speed index of algorithms switching compared with similar papers
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