Abstract
Increased buffer insertion along on-chip global lines and growing amounts of leakage power have resulted in buffer-based leakage emerging as one of the chief contributors to system leakage power. In this paper, a bus system prototype is implemented in an industrial 65-nm SOI technology and measured results show up to a 45% reduction in total bus system power and an average reduction of 2.4× in standby mode leakage power.
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