Dynamic virtual channel and index-based arbitration based Network on Chip router architecture

Abstract

Network-on-Chip (NoC) is a popular communication and interconnection structure for multi or many-core system-on-chip (SoC). It mainly consists of routers, network interfaces and communication links. It typically utilizes virtual channels (VCs) to improve wormhole routing among the SoC cores by enabling multiple packet flits to share NoC communication links. DAMQ (Dynamically Allocation Multi Queues) based VC organization has higher buffer utilization but it also has a few problems. We present a novel NoC router architecture that provides solutions to these problems. It utilizes dynamic VC based buffering and index based arbitration methodologies. Arbitration is a critical operation employed in NoC routers that may results in lower speed, weak fairness, and difficulties in pipelining. Our arbitration techniques used in the presented router architecture overcome these problems. We have simulated and implemented our 2D-mesh NoC router using System-Verilog. The experimental results confirm the efficiency of our proposed NoC router in terms of superior router power and ASIC area as well as its operating speed. Performance metrics for different NoC configurations are determined and evaluated for a variety of traffic patterns.