Adaptive VC Organization and Arbitration for Efficient NoC Design

Abstract

Network-on-Chip (NoC) has emerged as one of the main communication structure suitable for the interconnection of processing and other IP cores of a system-on-chip (SoC). An NoC typically utilizes virtual channels (VCs) to improve wormhole routing among the SoC cores by enabling multiple data packets to share a communication channel and to avoid deadlocks. Dynamically allocation multi queues based VC organization has higher buffer utilization but it also has some problems such as complexity, setup limitation, etc. Arbitration is also an important part of NoC routers. Past arbitration techniques have some problems that are related to lower speed, fairness, and router pipelining. We present a novel NoC router (RDQ-IRR-v2) architecture that incorporates some solutions to all of these problems. The router design utilizes adaptive VC buffering and index based arbitration techniques. The experiments and simulations indicate the efficiency of our proposed NoC router in terms of power consumption, chip area, frequency of router as well as latency and throughput related performance metrics in different NoC configurations and for various traffic patterns.