Dynamic simulation of migration induced failure mechanism in integrated circuit interconnects

Abstract

At the moment the miniaturisation of integrated circuits for consumer electronics means to decrease the size of Cu interconnects below 100nm, while a lifetime of 3–5years has to be guaranteed. For industrial and automotive applications wider Al interconnects (∼350nm) are used, but an extreme low rate of failures (0.1ppm) has to be reached to produce reliable end-products including dozens of components. A further progress in the development of high-end electronics and more complex industrial products needs a better prediction of possible failure mechanism and the related time to failure of the chosen technology. This investigation is focused on migration induced void formation and combines the results of process simulations, for the back end of line, (intrinsic pre-stress) with the dynamic simulation of the migration induced material movement in the interconnects. To minimise the gap between idealized simulations and reliability tests the grain structure of the Al and Cu lines, the interaction between electromigration and the mass flux due concentration gradients, as well as the different transport mechanism for grain boundary and interface diffusion were taken into account. For the surrounding metal of existing voids specific activation energies in dependence on the crystal orientation of the metal surfaces were given. As result a prediction of the point of failure and the void formation process will be given for the chosen back-end technologies.