Abstract
In this paper, we propose a reconfigurable architecture for discrete cosine transform (DCT) computation. The objective of the paper is to integrate the DCT computation in a complete embedded system based on ARM processors. Based on dynamic partial reconfigurable FPGAs, different versions of DCT computation are used to give adaptability and flexibility to the architecture. These adaptability responses to different service requirements at run time, such as image quality levels, and system performance. We also explore an efficient management of the reconfigurable area by adjusting the size of the reconfigurable region to the different variable sized hardware module related to the adaptable DCT IP core. The ZedBoard development kit based on the Xilinx Zynq-7000 was used in the study. The results of implementation offer a number of benefits such as optimized hardware resources utilization, efficiently handled the reconfigurable area and reduced reconfiguration time.
Published Version
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