Dynamic BTB Resizing for Variable Stages Superscalar Architecture

Abstract

To extract instruction level parallelism (ILP) and thread level parallelism (TLP), super scalar architecture has become commonly used for high-performance computers. While a deeper super scalar pipeline achieves a higher performance, it consumes a larger energy consumption. For the energy reduction of a deeply-pipelined processor, we have proposed a variable stage pipeline (VSP) architecture which reduces the energy consumption by dynamically unifying the pipeline stages according to behavior in a program. Because the pipeline structure alters after pipeline unification, hardware for extracting ILP and TLP also should be resized to balance the energy-performance trade-off. In this paper, we propose a dynamic branch target buffer (BTB) resizing technique into VSP implemented on a super scalar processor to reduce further energy consumption when the VSP unifies the pipeline stages. The proposed technique resizes the size of the BTB along with pipeline scaling. Our evaluation results show that using the proposed technique can reduce the BTB size to one-eight after pipeline unification with only 0.02% prediction accuracy degradation on the average compared with the baseline BTB. This results in 9.2% dynamic energy reduction of the processor core with a trivial performance loss. Furthermore, our technique reduces the leakage energy consumption in the BTB by 87.5% with a practical leakage control technique.