A CAM-Based Separated BTB for a Superscalar Processor

Abstract

In current super scalar processors, branch target buffer (BTB) is an important component for predicting branch target addresses. In deeper pipelines and large windows, BTB mis-prediction increases penalty. Hence, increasing the accuracy of BTB prediction became more important for enhancing the performance in current processors. This paper proposes a novel BTB that separates current BTB into conditional branch BTB (CBTB) and non-conditional branch BTB (NBTB) for increasing the accuracy of prediction. The CBTB uses the current BTB. The NBTB is added on the current BTB. For discussion the hardware size, we equips NBTB by two kind structures. One is static random access memory (SRAM) and the another is content addressable memory (CAM). The experiment results show that proposed BTB improved IPC about 3.12% by adding an optimum of 128 entries current BTB with CAM structure.