Abstract

Dealing with resource constraints is an inevitable feature of embedded systems. Power and performance are the main concerns beside others. Pre-silicon analysis of power and performance in today’s complex embedded designs is a big challenge. Although RTL (Register-Transfer Level) models are more precise and reliable, system-level modeling enables the power and performance analysis of complex and dense designs in the early design phase. Virtual prototypes of systems prepared through architectural simulation provide a means of evaluating non-existing systems with more flexibility and minimum cost. Efficient interplay between power and performance is a key feature within virtual platforms. This article focuses on dynamic voltage and frequency scaling (DVFS), which is a well-known system-level low-power design technique together with its more efficient implementations modeled through architectural simulation. With advent of new computing paradigms and modern application domains with strict resource demands, DVFS and its efficient hardware-managed solutions get even more highlighted. This is mainly because they can react faster to resource demands and thus reduce induced overhead. To that end, they entail an effective collaboration between software and hardware. A case review in the end wraps up the discussed topics.

Highlights

  • The miniaturization trend in semiconductor technology has increased the number of transistors on a die

  • This article focuses on dynamic voltage and frequency scaling (DVFS), which is a well-known system-level low-power design technique together with its more efficient implementations modeled through architectural simulation

  • A case study that refers to a very particular and unique work that combines DVFS, mixed criticality with strict timing requirements, and its hardware-managed solutions modeled with architectural simulation models wraps up the discussed topics in the end

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Summary

Introduction

The miniaturization trend in semiconductor technology has increased the number of transistors on a die. A case study that refers to a very particular and unique work that combines DVFS, mixed criticality with strict timing requirements, and its hardware-managed solutions modeled with architectural simulation models wraps up the discussed topics in the end. The purpose of the manuscript is to study DVFS and its architectural simulation models with an emphasis on hardware-managed solutions to reduce dynamic power consumption of modern complex embedded systems with strict timing constraints, while retaining performance. The aim is to review early-stage mechanisms and tools with which modern embedded systems are capable of providing a better solution to resource demands including power, performance, and timeliness

System-Level Low-Power Architectures
Embedded Systems and Energy
Sources of Power Dissipation
Energy-Efficient Design Techniques
Design Considerations When Using DVFS
Hardware-Managed DVFS
Modeling Hardware-Managed DVFS
System-Level Performance Modeling Techniques
Architectural Simulation
Modeling Scope
Modeling Details
Execution of Program Instructions
Simulation Platforms
DVFS Support within Simulation Platforms
Mixed-Criticality
Overviewon of the the Mixed-Criticality
Research on Mixed Criticality
Mixed-Criticality Task Model
Mixed-Criticality Scheduling Algorithms
Mixed Criticality and Energy Efficiency
Case Review
Hardware-managed
Findings
Conclusions
Full Text
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