Dummy Poly Gate Removal Scheme at FinFET

Abstract

High-K metal gate (HKMG) approach has been introduced to enhance the device performance via lowering device current leakage. Dummy poly gate removal (DPGR) process is introduced in HKMG process to form the metal gate with different work functions for n/p-MOS. However, the introduction of this technology does pose many new challenges to various fabrication processes, especially for etch process at 14nm node and beyond. In FinFET technology, ploy-si is removed simultaneously for both n-MOS and p-MOS. normally, the partial dry etch and partial wet etch scheme is adopted for less plasma damage. This paper will introduce full dry etch process to complete poly-si removal. This definitely requires soft etch process to avoid the damage of Fin top and channel while meeting all the physical targets.