Abstract
This paper presents a dual-gate junctionless FET (DGJLT) on SOI for enhanced analog/RF performance. The Si channel of device is sandwiched between the two gates placed in separate vertical trenches. The proposed structure is studied for moderately doped drain (MDD) and heavily doped drain (HDD) concentrations. The analog/RF performance parameters of both the configurations are analysed and compared using ATLASTM TCAD simulator. The simulation results reveal that the HDD-DGJLT provides superior performance as compared to MDD-DGJLT in terms of gm, fT and fmax. At a gate length of 20 nm, the HDD-DGJLT exhibits a peak gm, fT and fmax of 3102 μS/μm, 554 GHz and 875 GHz, respectively, which are significantly higher as compared to the reported DG-JLFETs in the literature. Therefore, the proposed HDD-DGJLT can be considered as a better choice for high frequency small signal applications.
Published Version
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