Dual Channel Multiplier for First-Order Piecewise Approximation for GPU

Abstract

This paper demonstrates an energy-efficient implementation of piecewise polynomial approximation to evaluate the complex functions of graphical processing units (GPUs). A novel approach is employed to implement the first-order piecewise approximation serially which leads to high savings in power and area. Dual channel multiplier (DCM) scheme is proposed to simplify the hardware architecture of the piecewise polynomial approximation. The proposed methodology is implemented with 90[Formula: see text]nm CMOS technology and it can perform different complex functions using a simple multiplier hardware structure. DCM achieves improvement in energy saving by up to 81% at a penalty cost of 10 clock cycles. Simulation results confirm that this work attains at least 83%, and 55% saving in power and area as compared to the traditional techniques, respectively. The proposed methodology can implement any degree of the piecewise polynomial approximation utilizing the DCM.