Abstract
Further device scaling below the 65nm node required the introduction of metal gates/high-k layers. This paper discusses the etching approaches for patterning TiN/Mo, TiN/MoOx and TiN/MoOxNy layers used in poly-silicon metal gate stacks. We found that for these Mo based layers, the dry etching using any Cl2/O2 ratio provoked a severe isotropic etching. HBr gas was used as a key component for controlling side-walls passivation. The MoOx and MoOxNy layers were more prone to lateral attack compared to Mo due to the intrinsic stoichiometric oxygen. A good selectivity towards the substrate was obtained using high O2 flows in Cl2/O2/HBr mixtures. Etching of the TiN layer was carried out with Ar/Cl2. This process was tuned by adding HBr depending on the metal gate stack, which suggests that TiN etching is highly influenced by the Mo layer nature (TiN/Mo, TiN/MoOx and TiN/MoOxNy). We have also compared the complete gate stack pattering characteristic when an oxide or an amorphous carbon hard mask has been used for pattern definition.
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