Drop impact reliability analysis of CSP packages at board and product levels through modeling approaches

Abstract

Chip scale package (CSP) and fine pitch ball grid array (BGA) packages have been increasingly used in portable electronic products such as mobile cell phones and PDA, etc. Drop impact which is inevitable during its usage could cause not only housing crack but also package to board interconnect failure, such as BGA solder breaks. Various drop tests have been used to ensure high reliability performance of packaging to withstand such impact and shock load. Due to extreme difficulty in directly measuring responses in solder joint during drop shock event, computer simulation based modeling approach has been increasingly played an important role in evaluating product reliability performance during product development. An advanced modeling technique with a comprehensive failure criterion including high strain rate effect needs to be developed to quantitatively evaluate package reliability performance especially in cross comparisons between different board and system level designs. In this paper, three drop tests have been modeled, namely, bare board drop, board with fixture drop or shock, and system level phone drop. Submodeling and explicit-implicit sequential modeling techniques are used to characterize the dynamic responses of CSP/BGA packages in different board designs. Failure criteria and effects of strain rate and edge support on BGA in multicomponent boards are also investigated. A validation test with data acquisition is used to correlate the test results with numerical results.