Drain–Erase Scheme in Ferroelectric Field-Effect Transistor—Part I: Device Characterization

Abstract

Ferroelectric-doped HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based ferroelectric field-effect transistors (FeFETs) are being actively explored as emerging nonvolatile memory devices with the potential for in-memory computing. In this two-part article, we explore the feasibility of FeFET-based 3-D NAND architecture for both in situ training and inference. To address the challenge of erase-by-block in NAND-like structure, we propose and experimentally demonstrate the drain-erase scheme to enable the individual cell's program/erase/inhibition, which is necessary for individual weight update in in situ training. We describe the device characterization of different drain- erase conditions and results in this article. The experimental conditions are characterized on 22-nm fully depleted silicon-on-insulator (FDSOI) and 28-nm high-k metal gate (HKMG) FeFET devices from GLOBALFOUNDRIES. With appropriate biasing, up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> ON/OFF ratio could be achieved by drain-erase. The 3-D NAND array architecture design and verification for in-memory computing will be described in Part II of this article.