Abstract
This paper proposes a new DPWM architecture that takes advantage of FPGApsilas advanced clock management capabilities. The feature used in this investigation is that the clock management system nowadays present in almost every FPGA allows fine phase shifting of the clock. This is not only true for high-end and expensive FPGAs. Using a low cost FPGA, like Xilinx Spartan-3, the clock can be phase shifted in steps that range from 30 to 60 ps. This opens new possibilities for pushing the limits of DPWM resolution. The experimental results show two alternative DPWMs that obtain a time resolution under 100 ps while maintaining high linearity and monotonic behavior.
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