DPLLs in Wireless Communication: Current State and Trends—A Literature Survey

Abstract

Communication technologies have seen massive growth over the past few decades. Though advanced features provided by contemporary 3G and 4G systems lead to increased popularity among masses`, providing satisfactory services remain an issue with user number and applications growing exponentially. Replacement approaches have already been devised including the testing of fifth-generation systems which promises to meet the ever-increasing demands of higher data rates with low latency and uniform coverage with decreasing constraints related to power and quality of service. In this scenario, phase-locked loop (PLL) receivers in many forms have started to receive greater attention. Since its first successful use in 1932, PLLs in varied incarnations including digital PLL (DPLL) have been accepted to be integral elements of communication setups. One of the major advantages of DPLL is its ability to ensure error minimization using a phase-dependent approach at the cost of increase in computational latency. A new class of designs has recently emphasized on minimizing the time delay in DPLL loop using different techniques to achieve time-efficient symbol recovery by parallelizing loop actions. Similarly, clustering techniques could be efficiently used for this purpose. A detailed survey on different aspects related to design of low latency DPLLs with acceptable error rates is presented here.