DPL-based novel CMOS 1-Trit Ternary Full-Adder

Abstract

ABSTRACT This paper presents a new high-speed, low-power, area-efficient 1-trit Ternary-Full-Adder (TFA) as a building block for wave-pipelined ternary-digital system design. Balanced input capacitance with structural symmetry makes Double Pass-transistor Logic (DPL) an ideal candidate for this, and is employed here hence. Design-strategy with working-principle is presented. The TFA is designed and optimised on normal-process-enhancement-type MOS devices that use BSIM4 model-parameters, on 1.0 V supply-rail at 27°C temperature. Simulations are carried out using Tanner EDA V.16. The ternary values ‘0’, ‘1’ and ‘2’ are coded with 0 V, 0.5 V and 1.0 V, respectively. The circuit is time-equalised through coarse and fine-tuning for all data paths from input-to-output to offer efficient wave-pipelining feature. The transient response from T-Spice simulation is validated for all test-patterns. Physical design of proposed TFA is completed using TSMC 65 nm Single-Poly-Double-Metal (SPDM) CMOS process-technology using Microwind3.1. After DRC, LVS and parasitic extraction, the post-layout simulation is done. PVT analysis with statistical PVT (Process-Voltage-Temperature) variation is used to find a worst-case speed-power response of the TFA. Propagation delay is examined for all test patterns and is found satisfactory ensuring effective wave-pipelining. Comparative study with recent candidate designs reveals nearly 21.43% PDP-reduction over the best reported.