Double strained Si channel heterostructure on insulator MOSFET in sub-100nm regime

Abstract

Incubating strain technology in MOSFET arena with, combination of strained Si, strained SiGe and relaxed SiGe forming a single or dual channel has been developed widely, while developing a novel sub-100nm MOSFET on double strained Si with strained SiGe sandwiched in between, forming a tri-channel MOSFET has been the focus in the present research. Double strained Si with strained SiGe channel MOSFET of 100nm and 50nm channel length has been compared leading to the attainment of eloquent drain current enhancement of ~41.3% associated with slightly higher drain induced barrier lowering for very short channel device of 50nm, which is attributed to the quasi-ballistic transport in the channel region. Simulation result showed improved maximum transconductance (gmmax) for 50nm compared to 100nm channel length MOSFET due to the velocity overshoot occurring in the channel region, indicating ~25% decrease in threshold voltage and band structures lowering due to the strain technology in short channel device has been analyzed.