Development of Tri‐Layered s‐Si/s‐SiGe/s‐Si Channel Heterostructure‐on‐Insulator MOSFET for Enhanced Drive Current

Abstract

Incubation of strain technology in the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) arena by developing heterostructure layers combined of Si and SiGe layers within the channel is employed widely. Development of a fully depleted novel device featuring a distinguished tri‐layer heterostructure channel consisting of mobility enriched double strained Si (s‐Si) layers sandwiching strained SiGe (s‐SiGe) in between has been the crux of this paper. The channel with s‐Si/s‐SiGe/s‐Si significantly enhances electron mobility in comparison to conventional device of s‐Si on relaxed SiGe channel, leading to improved device performance without implementing additional scaling. The tri‐layered channel and the conventional device are compared and eloquent drain current enhancement of 49% attained with minimal value of threshold voltage roll‐off with increased strain infusion within the channel region, which augments electron mobility in the s‐Si layers. Augmented maximum transconductance for sub‐50 nm channel length due to velocity overshoot enhancement of 119% in comparison to conventional device acquired lead to ≈25% decrease in threshold voltage by band structure lowering with the instigation of the strain technology in the short channel device attained. Hence, with higher carrier mobility and improved drive current double strained Si heterostructure on insulator (HOI) MOSFET device is designed and developed.