Double Junction Tunnel Using Si Nanocrystalline Layer for Nonvolatile Memory Devices

Abstract

A novel nonvolatile memory tunnel layer structure is proposed in which a Si nanocrystalline layer lies between double tunnel oxides. By Si nanocrystal size downscaling to 2 nm, the new double junction tunnel attains a remarkable 3×106 times retention improvement while keeping high-speed write/erase compared to single tunnel oxide. Based on Si nanocrystal size confirmation by transmission electron microscope (TEM), we show quantitatively that the advantage is due to Coulomb blockade and quantum confinement, and smaller Si nanocrystal will lead to greater improvement. We clarify a characteristic effect in double junction tunnel, tunnel penetration disappearance, which is extremely advantageous for nonvolatile memory applications and never occurs in other multilayer dielectrics structures. The double tunnel junction using Si nanocrystalline layer is very promising for future memory.