35 nm floating gate planar MOSFET memory using double junction tunneling

Abstract

It is shown that, for 35 nm gate length, a silicon nitride trap memory using double junction tunneling can retain more than 4 decades memory window for 10 years in less than 9 volts w/e voltage, where 1E+6 w/e cycle endurance is attained simultaneously. This is due to Coulomb blockade and quantum confinement in Si nanocrystals lying between double tunnel oxides, and further improvement is possible by Si nanocrystal scaling. Therefore, the double junction tunneling SiN memory is an excellent candidate for less than 35nm region future memory