Double Hamming distance‐based 2D reordering method for scan‐in power reduction and test pattern compression

Abstract

A double Hamming distance-based 2D reordering method is proposed for a test set with don't care bits (Xs) to reduce scan-in power and compress test patterns. In this method, the rows and columns in the test set are reordered sequentially so that similar rows or columns are aggregated together. Being different from other reordering-based methods, the authors' method reorders every two rows or columns with more identical bits closer in the whole reordering process, where more Xs are clustered. Each X is then replaced with 0 or 1 using minimum transition filling scheme to minimise '1-0' and '0-1' logical state transitions. A small number of the logic state transitions cause low switching activity, which not only reduces scan-in power consumption but also facilitates code-based test pattern compression. Experimental results show that their proposed method achieves peak and average power reductions of 18.01 and 12.97% compared to the state-of-the-art method, respectively. Furthermore, the compression ratio of alternating shifted frequency directed run-length coding is improved to 73.76% in average utilising their proposed method.