Double-Gate Negative-Capacitance MOSFET With PZT Gate-Stack on Ultra Thin Body SOI: An Experimentally Calibrated Simulation Study of Device Performance

Abstract

In this paper, we propose and investigate the high-performance and low-power design space of nonhysteretic negative capacitance (NC) MOSFETs for the 14-nm node based on the calibrated simulations using an experimental gate-stack with PZT ferroelectric to obtain the NC effect. All necessary parameters are extracted by carefully characterizing experimentally fabricated ferroelectric capacitors, to ensure realistic simulation results. The ferroelectric thickness obtained by the proposed approach leads to the maximum enhancement in the nonhysteretic operation of NC transistors. We report a clear and significant double improvement in: 1) subthreshold swing and 2) gate overdrive, using the NC effect. Simulations using Silvaco TCAD coupled with a realistic Landau model of ferroelectrics demonstrates that a 14-nm node ultrathin body and box fully depleted silicon-on-insulator FET can operate at 0.26 V instead of 0.9 V gate voltage using the NC effect, with an average subthreshold swing of 55 mV/decade at room temperature. The double-gate structure is proposed to overcome the large mismatch between the ferroelectric and MOS capacitor to enhance the NC effect and reduce the ferroelectric’s optimized thickness. A 14-nm node double-gate negative capacitance FET can operate at 0.24 V gate voltage with an average subthreshold swing of 45 mV/decade.