Abstract
Double-Gate MOSFET (DGFET) is one of the promising technologies for sub-50 nm transistor design. To accommodate future technology nodes, transistor dimensions have to be reduced which leads to several disadvantages in transistor function. By using double-gate transistors many of these problems can be resolved to give efficient circuit performance. As we go for further scaling down, use of double-gate transistors in logic gate design gives significant improvements over conventional single-gate CMOS design. These are observed by comparing the designs of a full-adder circuit with single-gate and double-gate transistors using HSPICE simulations.
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