Abstract
This paper presents design of a Double Gate (DG) heterostructure based tunnelling FET with Subthreshold less than 60 mV/decade. The designed DG-FET has attained the sub-threshold slope (SS) of 51.5 mV/decade and provides on-current of 1.93 nA/μm 2 for Si3N4 as tunnel dielectric material. Due to non-similar doping of the regions there is no ambipolarity in the device characteristics which further reduces the off currents by 9.29fA/μm. The on-current in this structure can be enhanced by increasing the height of the source region. Low threshold voltage (Vth) is achieved due to the band to band tunnelling through thin dielectric. At 4nm the threshold voltage (Vth) is 0.301 V and at 1 nm it lower downs to 0.131 V but at the cost of increased subthreshold slope. The designed structure successfully achieves a high Ion/Ioff ratio of 2.07 x 10 5 for a gate dielectric thickness of 4nm. It has been observed that as thickness of gate dielectric is scaled down to 1nm, the Ion/Ioff ratio degrades to 1.538 x 10 2 due to sharp increase in Ioff current.
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