Dopant segregated Schottky barrier nanowire transistors using low-temperature microwave annealed ytterbium silicide

Abstract

Thermal budget is one of the major concerns to fabricate three-dimensional (3D) transistors using practical CMOS technologies. In this work, low-temperature microwave annealing is utilized for the fabrication of dopant segregated Schottky barrier gate-all-around nanowire transistors. Low electron Schottky barrier of ytterbium silicide was combined with Phosphorus segregation to form metallic source/drain for high-performance N-channel nanowire transistors. Effects of microwave annealing on metal silicidation as well as dopants segregation are intensively examined by comparing with those using rapid thermal annealing. The minimum microwave power of 200% and processing time of 200 s can be used during annealing to minimize the thermal energy while retaining sufficient activation and silicidation. Experimental results show that the microwave annealing produce better electrical characteristics of dopant segregated Schottky barrier nanowire transistors, serving as a promising approach to fabricate metallic source/drain nanowire transistors for future 3D integration of CMOS technologies.