Domain Decomposition Methods for Semiconductor Device Problems On a Cray S-MP

Abstract

A domain decomposition technique for the numerical solution of one-dimensional semiconductor device equations is implemented on a CRAY S-MP System 500 Matrix Coprocessor with 28 processing elements. A total work expression is constructed for comparison with the actual computing time of the parallel tech nique. We examine the behavior of the numerical method by using different configurations of the pro cessing elements within the parallel machine. We per form experiments on a number of devices including p-n junctions and thyristors.