DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM

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This paper presents a novel design flow and algorithms for simultaneous power-stability optimization of nano-CMOS static random access memory (SRAM) circuits. A 45 nm single-ended seven transistor SRAM has been used as case study. The SRAM cell is subjected to a dual-V Th assignment based on a novel combined Design of Experiments and Integer Linear Programming (DOE-ILP) approach, resulting in 50.6% power reduction (including leakage) and 43.9% increase in the read static noise margin over the baseline design. The process variation analysis of the optimized cell is performed considering the variability effect in twelve device parameters. An 8 x 8 array is constructed to show the feasibility of the proposed SRAM cell. To the best of the authors' knowledge, this is the first research reporting the use of DOE and ILP for optimization of conflicting targets of power and stability in SRAM.