D-logic exploration: Rapid search of Pareto fronts during architectural synthesis of custom processors

Abstract

Searching for a superior architecture in the design space of data paths during architectural synthesis of application specific (custom) processors is not a trivial task. This requires simultaneously resolving multiple conflicting design objectives as well as efficient management of orthogonal issues such as exploration speed and quality of result. This paper introduces a novel methodology using Dominance criterion (D-logic) to efficiently combat the problem of design space exploration (DSE) of functional resources during architectural synthesis. Novel D-logic models for power, area and execution time parameters have been proposed in this paper that deterministically resolves the orthogonal issues encountered during DSE, thereby resulting into a set of non-dominated Pareto fronts. Finally the optimal point from the Pareto fronts is selected based on the final user objective. The proposed method is several orders of magnitude faster and superior in terms of searching Pareto fronts and indentifying an optimal solution than most of the current stochastic techniques employed for DSE in architectural synthesis. This has been confirmed through the results obtained after comparison with a recent genetic based DSE technique where average improvement in quality of results (QoR) achieved is >9% (in terms of power and execution time) and average reduction in exploration time is >90%.