Dithering performance of oversampled ADC systems affected by hysteresis

Abstract

This paper addresses the problem of hysteresis in ADC systems and the improvement that can be obtained in the performance of such systems with the use of dithering and oversampling. The paper starts with an analysis of ADC hysteresis errors considering their effect on the quantization error and effective number of bits of an ADC system. It concludes with a study of the improvements obtained using dithering in over sampled ADC systems with hysteresis errors. Special attention is paid to the effect of different time sequences of a deterministic dither signal. Experimental results that validate theoretical predictions are also presented.