A 32GS/s 8-bit time-interleaved ADC system with 16GHz wideband RF front-end and embedded fully-blind digital calibration

Abstract

This paper implements a time-interleaved ADC (TI-ADC) system with embedded 16GHz wideband track-hold (T/H) front-end. The TI-ADC is characterized with 32GS/s total sampling rate, by time-interleaving 16-channel sub-ADCs with 2GS/s individual sampling rate and 8-bit resolution. A digital blind post-calibration technique based on frequency domain analysis of the TI-ADC output is proposed, which is characterized using a comprehensive TI-ADC behavioral model. The model takes into account the timing, gain and offset mismatch errors. All the three mismatch errors are characterized using the specific basis functions. Without the need of training sequence, a blind calibration model is developed during an iterative loop to extract the mismatch errors, which are subtracted from the measured TI-ADC output successively. A maximum of 3-bit improvement for the effective number of bit (ENOB) has been achieved, resulting in a 6.5 bit ENOB at low-end frequency and 4.5 bit ENOB at high-end frequency. Further, the proposed technique is also effective to wideband signal's sampling.