Abstract
To investigate the highly boron-doped SiO/sub 2/ film, p/sup +/ polysilicon-gate PMOSFETs and capacitors were fabricated using the same process as is used for surface-channel-type n/sup +/-gate devices, except for the gate-type doping. After the application of negatively biased Fowler-Nordheim (FN) stress, it was found that positive charges accumulate near the silicon/SiO/sub 2/ interface and electrons accumulate near the polysilicon/SiO/sub 2/ interface in p/sup +/-gate capacitors. DC hot carrier stress was applied to both PMOSFET gate types. The p/sup +/ gate's stress time dependence of I/sub sub/ is smaller than that of the n/sup +/ gate, and the electric field near the drain in the p/sup +/-gate PMOSFET was found to be more severe than that of the n/sup +/-gate device. The subthreshold slope of the p/sup +/-gated PMOSFET was improved and then degraded during the hot carrier stressing, while that of the n/sup +/-gated device did not significantly change. The actual change of V/sub th/ was larger than the value derived from Delta /sub gm/ using the channel-shortening concept. The idea of widely spreading and partially compensated electron distribution along with source-drain direction in the SiO/sub 2/ film, which assumes the existence of trapped holes in the p/sup +/-gate PMOSFET, is proposed to explain these phenomena.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
Published Version
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