Abstract

A versatile compact technique for calculating dynamic avalanche breakdown conditions in the case of p+nn0(p0)pn+ bipolar structures with distributed microgates cut off in a resistively loaded circuit is suggested. These conditions determine the breakdown-limited ultimate switching power of a specific device. Examples of calculating the current, voltage, and power boundaries of the safe operating area for Si- and 4H-SiC-based structures are given. It is found that structures with gates extracting minority carriers having a higher impact ionization coefficient (electrons from the p0-base for silicon or holes from the n0-base for 4H-SiC) are most prone to breakdown. On the contrary, structures with gates of the opposite type, i.e., those extracting holes from the p0-base for Si or electrons from the n0-base for 4H-SiC (such structures have not yet found wide application), are most stable against breakdown. It is found that implementation of such structures for Si switches with switching voltage Umax= 5–7 kV may raise the maximal power per unit area from today’s ∼200 kW/cm2 to a new theoretical level of 0.7–1.0 MW/cm2. For 4H-SiC switches with Umax = 4.5–10.0 kV, a new level can be increased to 200 MW/cm2 or higher.

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