Abstract
InAs nanofins were prepared on a nanopatterned Si (001) substrate by metal-organic vapor-phase epitaxy. The threading dislocations, stacked on the lowest-energy-facet plane {111}, move along the SiO2 walls, resulting in a dislocation reduction, as confirmed by transmission electron microscopy. The dislocations were trapped within a thin InAs epilayer. The obtained 90-nm-wide InAs nanofins with an almost etching-pit-free surface do not require complex intermediate-layer epitaxial growth processes and large thickness typically required for conventional epitaxial growth.
Highlights
The semiconductor industry has followed Moore's law for over 30 years with gate dimensions of transistors approaching the nanometer scale (
For a zinc-blende structure deposited on a diamond structure, the dislocations generated near the InAs/Si interface, such as mistfit dislocations, threading dislocations, and antiphase domain boundaries, are annihilated or multiplied during the epitaxial process [6,7,8,9,10,11,12,13,14,15,16,17,18,19]
A large number of dislocations were generated at the InAs/Si interface; the dislocation density is above 109 cm−2
Summary
The semiconductor industry has followed Moore's law for over 30 years with gate dimensions of transistors approaching the nanometer scale (
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