Dislocation reduction in HgCdTe grown on CdTe/Si

Abstract

Bulk-grown CdZnTe (Zn = 3%) substrates are the natural choice for HgCdTe epitaxy since it is lattice matched to long wave LW-HgCdTe alloy. However, lack of large area CdZnTe substrates, high production costs, and more importantly, the difference in thermal expansion coefficients between CdZnTe and silicon Read out Integrated Circuits (ROIC) are some of the inherent drawbacks of CdZnTe substrates. Consequently, Hg 1-x Cd x Te detectors fabricated on silicon substrates are an attractive alternative. Recent developments in the molecular beam epitaxy (MBE) buffer layer growth technology on Si substrates has revolutionized the HgCdTe research and offered a new dimension to HgCdTe-based IR technology. Si substrates provide advantages in terms of relatively large area (3 to 6-inch diameter is easily obtained) compared to CZT substrate materials, durability during processing, and reliability to thermal cycling. Innovations in Si-based composite substrates made it possible to fabricate very large-format IR arrays that offer higher resolution, low-cost arrays and more dies per wafer. Between Si substrates and HgCdTe has large lattice mismatch of 19%. This leads to dislocation densities of low-10 7 cm -2 for optimal growth of HgCdTe on silicon-based substrates as compared to the mid-10 4 cm -2 dislocation density of HgCdTe grown on CdZnTe. This paper present dislocation reduction by two orders of magnitude using thermal cycle anneal under Hg environment on HgCdTe grown on Si substrates and as well as defect reduction in Cd(Se)Te buffer layers grown on Si Substrates.