Discussion group summary gate oxide reliability

Abstract

Scaling of CMOS technologies beyond the 90 nm node requires the reduction of the gate Dielectric thickness down to an Equivalent Oxide Thickness (EOT) of ˜ 1 nm which will either Be realized with SiON or high-k gate dielectrics. Both scenarios, the further scaling of SiON gate Dielectrics or the introduction of high-k dielectrics, bring various critical reliability challenges With it and need to be tackled in order to meet the stringent reliability reliability requirements of future CMOS technologies. Each attendee of the discussion group was asked to complete a questionnaire on some of the key Gate oxide reliability challenges for either SiON or high-k gate dielectric systems. A few selected Topics of the questionnaire were then discussed in detail and a summary of these topics is given Below for SiON and high-k dielectrics separately.