Direct Synthesis Based PID Controller Design for Time-Delayed Unstable Processes in Parallel Control Structure

Abstract

In this paper, a proportional–integral–derivative controller design for unstable time-delay system in the parallel control structure is proposed. The parallel control structure has two separate controllers for the set-point tracking and the load disturbance rejection. The two proposed controllers are designed through direct synthesis approach by selecting the separate closed-loop reference model for the set-point and the load disturbance response. The proposed design methods are applicable for both the low-order and the high-order unstable processes without model reduction in the higher-order process. The effectiveness of the proposed methods is demonstrated through simulation of different examples and comparison with the recently reported methods in the literature.