Abstract
Silicon semiconductor-insulator-semiconductor (SIS) structures with high-k dielectrics are a promising new material for photonic and CMOS integrations. The “diode-like” currents through the symmetric atomic layer deposited (ALD) HfO2/Al2O3/HfO2… nanolayers with a highest rectification coefficient 103 are observed and explained by the asymmetry of the upper and lower heterointerfaces formed by bonding and ALD processes. As a result, different spatial charge regions (SCRs) are formed on both insulator sides. The lowest leakages are observed through the stacks, with total Al2O3 thickness values of 8–10 nm, which also provide a diffusive barrier for hydrogen. The dominant mechanism of electron transport through the built-in insulator at the weak field E < 1 MV/cm is thermionic emission. The Poole-Frenkel (PF) mechanism of emission from traps dominates at larger E values. The charge carriers mobility 100–120 cm2/(V s) and interface states (IFS) density 1.2 × 1011 cm−2 are obtained for the n-p SIS structures with insulator HfO2:Al2O3 (10:1) after rapid thermal annealing (RTA) at 800 °C. The drain current hysteresis of pseudo-metal-oxide-semiconductor field effect transistor (MOSFET) with the memory window 1.2–1.3 V at the gate voltage |Vg| < ±2.5 V is maintained in the RTA treatment at T = 800–900 °C for these transistors.
Highlights
To minimize the leakage currents through the SIS structure, a 20-nm-thick alumina layer was firstly investigated as an insulator after different thermal treatments due to its high bandgap and amorphous phase stability [26,27,28]
In the inset are the measurement scheme and the layers of the n-SIS structure, where the bonding interface is indicated by a red line; (b) C-V plots of the MIS structure with high-k insulator Al2 O3 after the final FA at 1000 ◦ C for 1 h and top Si layer etching
The reason for the diode-like characteristics in symmetrical SIS structures is explained by the asymmetry of the upper and lower heterointerfaces formed by the silicon bonding to the high-k insulating layer and atomic layer deposited (ALD)
Summary
The high energy efficiency of optical switches based on semiconductorinsulator-semiconductor (SIS) structures has been reported, reaching femto- and even attojoules per operation when using a design of hybrid structures based on III-V/Si semiconductor pairs [1,2,3,4,5]. The development of more energy-efficient switches, compared to thermo-optical or MEMS devices, means real progress in the implementation of fast intrachip communication with switch frequencies of up to 200 GHz [4,5,6,7,8], and perspectives in building deep learning artificial neural networks based on ferroelectric transistors (FeFET), optical or quantum gates [9,10] compatible with the industrial CMOS technology. Hybrid III-V/Si structures noticeably increase the complexity of mass production of integral circuits (ICs) by the industrial CMOS silicon technology. The development of all silicon-based switches is a task of current interest
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