Digital Synthesizer/Mixer With Hybrid CORDIC–Multiplier Architecture: Error Analysis and Optimization

Abstract

This paper describes a novel architecture for digital synthesizer/mixer (DSM). The operation performed by a DSM corresponds to a rotation of the input vector in the complex plane. The proposed architecture divides this rotation into three subrotations. The first one uses a few CORDIC stages, in which the rotation directions are in parallel computed with the help of a small lookup table. The CORDIC algorithm is employed also in the second subrotation, where the rotation directions are readily available after a simple recoding of the bits of the residual angle. The final rotation is multiplier based to reduce circuit latency and increase performances. A detailed error analysis and sizing methodology is given in this paper. It is shown that different versions of the architecture can be conceived by varying the dimensions of the second block and the topology of the third block. The proposed architecture exhibits very good performances, owing to the efficient carry-save implementation of CORDIC datapaths, the reduced lookup table, and the small size of multipliers. Implementations in a 0.25- mum CMOS technology are presented in order to demonstrate the design methodology and to investigate the implementation tradeoffs.