Design and Implementation of High Frequency Functional Signal Generator using DDFS based on 16-stage pipelined CORDIC architecture

Abstract

Frequency synthesizer has been used in numerous communication applications. This is acknowledged as the heart of the electronics systems. Numerically controlled oscillator (NCO) is the primary part of this frequency synthesizer, which helps in generating high precision & high frequency signal. One of the best suited methods to empower the NCO is CORDIC algorithm. CORDIC (Coordinate Rotation Digital Computer) algorithm is one of the well-known methods used for the trigonometric & arithmetic calculation and applications of digital signal processing. This algorithm can work with higher efficiency for the signal generation & hardware utilization. CORDIC architecture is used in the NCO, which is the central part of DDFS (Direct Digital Frequency Synthesis) to produce analog signal. Here in this paper, a sinusoidal waveform generator is implemented using an efficient 16-stage pipelined CORDIC architecture with a very small look-up table (LUT). The architecture is designed, and its RTL simulation is carried out using Xilinx Vivado. The purpose of the work is to improve the output frequency and the accuracy. The architecture had been implemented on a Xilinx Spatran-6 (XC6SLX9) FPGA & the final results showed that the proposed pipelined architecture is capable of generating a maximum output frequency of 157.684 MHz with less than 1% (approximately 0.34%) of error.