Digital SiPM channel integrated in CMOS 65 nm with 17.5 ps FWHM single photon timing resolution

Abstract

Single photon avalanche diodes (SPAD) are detectors used for applications requiring high timing resolution and single photon sensitivity. Medical imaging modalities such as positron emission tomography benefit from higher timing resolution enabling time-of-flight (ToF) measurements. One of the current challenge in the development of SiPM detectors is combining both high photodetection efficiency (PDE) and high single photon timing resolution (SPTR). Although SiPM have a high fill factor, they are limited for sub-10 ps FWHM SPTR for two reasons: the high output capacitance directly affects the rise time and a timing skew is associated with the SPAD position in the array. The proposed solution to obtain ToF capabilities with both high SPTR and PDE is to make a 3D digital SiPM where every SPAD is individually connected to a quenching circuit (QC) and a time-to-digital converter (TDC). While the 3D integration process is underway, we designed and tested a 2D version of a single channel of the detector composed of a SPAD, a QC and a TDC in TSMC CMOS 65 nm. This paper presents a SPAD and QC with 9 ps FWHM SPTR and a chain composed of a SPAD, a QC and a TDC with 17.5 ps FWHM SPTR.